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DATA SHEET
DUAL, 1-TO-1Integrated DIFFERENTIAL-TOCircuit Systems, Inc. LVCMOS TRANSLATOR/BUFFER
GENERAL DESCRIPTION
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Features
* Two LVCMOS / LVTTL outputs * Two differential CLKx, nCLKx input pairs * CLK, nCLK pairs can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency: 350MHz (typical) * Output skew: 60ps (maximum) * Part-to-part skew: 500ps (maximum) * Additive phase jitter, RMS: 0.14ps (typical) * Small 8 lead SOIC package saves board space * 3.3V operating supply * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS-compliant packages
ICS83023I ICS83023I
The ICS83023I is a dual, 1-to-1 Differential-toIC S LVCMOS Translator/Fanout Buffer and a memHiPerClockSTM ber of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The differential inputs can accept most differential signal types (LVDS, LVHSTL, LVPECL, SSTL, and HCSL) and translate into two single-ended LVCMOS outputs. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space.
BLOCK DIAGRAM
CLK0 nCLK0 CLK1 nCLK1 Q0
PIN ASSIGNMENT
CLK0 nCLK0 nCLK1 CLK1 1 2 3 4 8 7 6 5 VDD Q0 Q1 GND
Q1
ICS83023I
8-Lead SOIC 3.8mm x 4.8mm x 1.47mm package body M Package Top View
83023AMI
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IDTTM / ICSTM DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER 1
ICS83023I
ICS83023I Circuit DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Integrated
ICS83023I
Systems, Inc.
DUAL, 1-TO-1 TSD DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8 Name CLK0 nCLK0 nCLK1 CLK1 GND Q1 Q0 VDD Input Input Input Input Power Output Output Power Type Pullup Pullup Description Inver ting differential clock input. Inver ting differential clock input. Power supply ground. Single clock output. LVCMOS / LVTTL interface levels. Single clock output. LVCMOS / LVTTL interface levels. Positive supply pin. Pulldown Non-inver ting differential clock input.
Pulldown Non-inver ting differential clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance Test Conditions Minimum Typical 4 VDD = 3.6V 23 51 51 7 Maximum Units pF pF k k
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IDTTM / ICSTM DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER 2
ICS83023I
ICS83023I Circuit DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Integrated
ICS83023I
Systems, Inc.
DUAL, 1-TO-1 TSD DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO 4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V
Package Thermal Impedance, JA 112.7C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V0.3V, TA = -40C TO 85C
Symbol VDD IDD Parameter Positive Supply Voltage Positive Supply Current Test Conditions Minimum 3.0 Typical 3.3 Maximum 3.6 20 Units V mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V0.3V, TA = -40C TO 85C
Symbol VOH VOL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Test Conditions Minimum 2.6 0.5 Typical Maximum Units V V
NOTE 1: Outputs terminated with 50 to VDD/2. See Parameter Measurement Section, 3.3V Output Load Test Circuit.
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V0.3V, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 CLK0, CLK1 Test Conditions VIN = VDD = 3.6V VIN = VDD = 3.6V VIN = 0V, VDD = 3.6V VIN = 0V, VDD = 3.6V -150 -5 1.3 VDD - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; GND + 0.5 VCMR NOTE 1, 2 NOTE 1: For single-ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
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IDTTM / ICSTM DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER 3
ICS83023I
ICS83023I Circuit DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Integrated
ICS83023I
Systems, Inc.
DUAL, 1-TO-1 TSD DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Test Conditions Minimum 1.8 Typical 350 2.1 2.4 60 500 Maximum Units MHz ns ps ps ps 400 400 55 57 ps ps % %
TABLE 4. AC CHARACTERISTICS, VDD = 3.3V0.3V, TA = -40C TO 85C
Symbol Parameter fMAX tPD t sk(o) t sk(pp) t ji t tR tF odc Maximum Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise Time Output Fall Time Output Duty Cycle 100MHz, Integration Range (637kHz-10MHz) 0.8V to 2V 0.8V to 2V f 166MHz
0.14 100 100 45 25 0 250 50
f > 166MHz 43 50 All parameters measured at fMAX unless noted otherwise. See Parameter Measurement Information. NOTE 1: Measured from the differential input crossing point to VDD/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. Input clocks are phase aligned. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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IDTTM / ICSTM DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER 4
ICS83023I
ICS83023I Circuit DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Integrated
ICS83023I
Systems, Inc.
DUAL, 1-TO-1 TSD DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a
0 -10 -20 -30 -40 -50 -60
ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 100MHz
(12kHz to 20MHz) = 0.14ps typical
SSB PHASE NOISE dBc/HZ
-70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated
above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
83023AMI
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IDTTM / ICSTM DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER 5
ICS83023I
ICS83023I Circuit DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Integrated
ICS83023I
Systems, Inc.
DUAL, 1-TO-1 TSD DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V 0.15V VDD
VDD
Qx
SCOPE
nCLK
LVCMOS
GND
V
CLK
PP
Cross Points
V
CMR
-1.65V 0.15V
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
V
Qx
DD
PART 1 Qx
V
DD
2
2
V
Qy
DD
PART 2 Qy
V
DD
2 tsk(o)
2 tsk(pp)
OUTPUT SKEW
nCLK0, nCLK1 CLK0, CLK1
PART-TO-PART SKEW
V Q0, Q1
DD
2
t PW
Q0, Q1
VDD 2 t
t
PERIOD
PD
odc =
t PW t PERIOD
x 100%
PROPAGATION DELAY
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
2V 0.8V tR
2V 0.8V tF
Clock Outputs
OUTPUT RISE/FALL TIME
83023AMI
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IDTTM / ICSTM DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER 6
ICS83023I
ICS83023I Circuit DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Integrated
ICS83023I
Systems, Inc.
DUAL, 1-TO-1 TSD DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached.
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IDTTM / ICSTM DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER 7
ICS83023I
ICS83023I Circuit DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Integrated
ICS83023I
Systems, Inc.
DUAL, 1-TO-1 TSD DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
faces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input inter-
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE
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ICS83023I
ICS83023I Circuit DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Integrated
ICS83023I
Systems, Inc.
DUAL, 1-TO-1 TSD DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
RELIABILITY INFORMATION
TABLE 5. JAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83023I is: 416 Pin-to-pin compatible with MC100EPT23
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ICS83023I
ICS83023I Circuit DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Integrated
ICS83023I
Systems, Inc.
DUAL, 1-TO-1 TSD DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC
TABLE 6. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
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ICS83023I
ICS83023I Circuit DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Integrated
ICS83023I
Systems, Inc.
DUAL, 1-TO-1 TSD DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Package 8 lead SOIC 8 lead SOIC Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS83023AMI ICS83023AMIT ICS83023AMILF ICS83023AMILFT Marking 83021AMI 83021AMI 83023AIL 83023AIL
8 lead "Lead-Free" SOIC 8 lead "Lead-Free" SOIC
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industiral applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83023AMI
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ICS83023I
ICS83023I Circuit DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Integrated
ICS83023I
Systems, Inc.
DUAL, 1-TO-1 TSD DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Date 09/09/02
REVISION HISTORY SHEET Rev A Table 7 T2 T4 B T7 B T7 Page 11 1 2 4 5 7 8 11 11 Description of Change Ordering Information Table - corrected Par t/Order Number for Tape & Reel to read ICS83023AMIT from ICS83023AMI. Features Section - added Additive Phase Jitter and Lead-Free bullets. Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical. AC Characteristics Table - added Additive Phase Jitter row. Added Additive Phase Jitter Plot. Added Recommendations for Unused Input and Output Pins. Added Differential Clock Input Interface. Ordering Information Table - added Lead-Free Par t Number and Note. Update datasheet format. Ordering information Table - added Lead-Free marking.
12/12/05
1/18/08
83023AMI
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ICS83023I
ICS83023I ICS252 DUAL, PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER FIELD 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
TSD TSD
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Corporate Headquarters
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Asia Pacific and Japan
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Europe
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(c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA XX-XXXX-XXXXX

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